Office 2010 Understanding the VXI VME Interrupt an

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from an engineer Comprehension the VXI/VME Interrupt and Signal Acknowledge Cycle
The VME bus specification defines the Priority Interrupt Bus to ensure a VME system can
asynchronously request service from a controller. This offers a VME/VXI device a means of acquiring
the controller’s focus at any time.
A VXI/VME bus method has seven interrupt lines physically linked to all slots inside the chassis.
This document addresses interrupts on equally VME and VXI programs.
Interrupt line 7 has the greatest priority, and interrupt line one has the lowest priority.
Furthermore to the actual interrupt lines, the Priority Interrupt Bus also consists of the
daisy-chained interrupt acknowledge signal and elements of the Knowledge Transfer Bus
(the info lines, the information acknowledge line, along with the decrease three address lines).
The table under summarizes every signal used in the Priority Interrupt Bus and
summarizes the function of each signal. A gadget that requests support by asserting
one of your interrupt lines is called an interrupter. A functional gadget called
an interrupt handler services the interrupt. There could be greater than 1
interrupt handler in a very VXI/VMEbus program. Nationwide Instruments embedded controllers
and external MXI bus controllers permit you to configure numerous interrupt handlers
(from one to seven).
Table I. Priority Interrupt Bus Signals

Signal
Function
IRQ1*-IRQ7*
An interrupter uses this signal to indicate that it is requesting services.
IACK*
An interrupt handler uses this signal to indicate that it has received an interrupt and is ready to receive a status/ID that will tell the handler how to proceed with servicing the interrupt.
IACKIN*/
IACKOUT*
A module receives the IACK* on IACKIN*. It places a status/ID on the bus if the interrupt level being serviced matches the module’s interrupt level and if the gadget is interrupting. Otherwise, the module passes the signal on using IACKOUT*.
A01-A03
The interrupt handler asserts these lines with the value corresponding to
the interrupt level being serviced.
D00-D31
The interrupter being serviced places the status/ID on these lines once IACK* has been received.
DTACK*
The interrupter uses this signal to indicate that its status/ID is asserted on the data lines.

A far more detailed explanation of what happens within the interrupt cycle is outlined below.
A gadget that requests support by asserting a single of the interrupt lines is called an interrupter. A purposeful system called an interrupt handler companies the interrupt. There can be a lot more than one interrupt handler in a very VXI/VME bus system. However, there can only be one particular interrupt handler per interrupt level within the system. Countrywide Instruments embedded controllers and exterior MXI bus controllers enable you to configure several interrupt handlers (from 1 to 7).
Therefore, two types of interrupt handler techniques are possible:
A single handler technique A distributed program
Inside a single handler program, 1 interrupt handler device services all interrupt lines. In a distributed system, there are two or more handlers, every single servicing an exclusive subset of the seven interrupt lines. Most systems are single handler techniques, where the method controller handles all interrupt lines within the chassis. It is possible for VXI devices to act as programmable interrupt handlers, but this is not very common. The Resource manager detects programmable VXI interrupt handlers and uses information stored within the device’s configuration registers to assign the interrupt levels that will be handled by the VXI system. Note that VME devices do not define a standard set of configuration registers - you must use Test and Measurement Explorer or VXI Edit/vxitedit to enter any configuration information associated with the VME device.
There are two types of interrupters:
Release On ACKnowledge (ROAK) Release On Register Access (RORA)
Most VXI and VME instruments fall under the ROAK category and the sequence of events described under is only applicable to ROAK devices.
The Sequence of Events During an Interrupt (IACK*) Cycle
After a device asserts an interrupt,Office Ultimate 2007 Product Key, it waits for a response from the interrupt handler. When the interrupt handler detects that an interrupt line has been asserted, the interrupt handler asserts the IACK* (interrupt acknowledge) signal. It also sets the decrease three tackle lines A01 – A03 to indicate which interrupt line it is trying to acknowledge with the IACK* signal. The IACK* line that the handler drives is connected towards the IACKIN* pin of slot 0 inside the chassis (Slot one in VME bus systems). If the module inside the first slot is not asserting the interrupt line being acknowledged,Office 2010, the module must propagate the IACK* signal to its IACKOUT* pin, which is connected to your next slot’s IACKIN* pin. The propagation from the IACK* signal from slot to slot continues until the IACK* signal reaches the first module that is interrupting on the line being acknowledged. When the interrupter sees IACK*, it places its status/ID on the data/bus.
The interrupt handler reads the status/ID. Because the interrupt lines are open collector lines, over 1 gadget can assert the same interrupt line at the same time. Therefore, the module asserting the interrupt does not propagate the IACK* signal. This action prevents other devices that are interrupting on the same line from getting the IACK* signal and attempting to respond at the same time. After the interrupt handler solutions the interrupter, the interrupter releases the line. If other devices are interrupting on the same line, the handler then begins another interrupt acknowledge cycle to service the next interrupter on that line. The following figure illustrates the interrupt acknowledge daisy-chain.
Figure 1. Interrupt Acknowledge Daisy-Chain
Note: RORA devices require you to read/write a system particular register in order to complete the interrupt acknowledge cycle.
In this figure, the gadget in slot 4 has asserted an interrupt. The figure shows that if greater than a single device asserts the same interrupt line, the device closest to slot 0 (slot one in VME) has the greatest priority for interrupt support because it receives the IACK* signal first. The next closest device has the next greatest priority, and so on. It is important to remember that the IACK daisy chain must be related across unoccupied backplane slots, or else interrupts coming from devices to your right of the empty slot will not be acknowledged. Most chassis have jumperless backplanes where this daisy-chain connection happens automatically. However, on older backplanes that are jumpered, jumpers must be employed to connect the IACK daisy chain across unoccupied slots. On jumpered backplanes, you should also pull the jumpers from the occupied slots to ensure that the IACK daisy-chain is not mistakenly related through the slot containing the interrupter.

Status/ID Value
The status/ID in most VME systems is an 8-bit value. In VXI programs, the status/ID is either a 16-bit or 32-bit status/ID value. Message-Based devices that have interrupter capability must return at least a 16-bit status/ID with an optional 32-bit value. Currently, 32-bit status/IDs are uncommon. In VME programs, the status/ID is usually a vector. The processor uses this vector to calculate an deal with to a position in an interrupt jump table. The entry in that table is the tackle with the start from the interrupt services routine.
Therefore, when the processor handles the interrupt and receives the status/ID, it jumps directly towards the beginning from the interrupt support routine and executes the interrupt support routine code. The method integrator installs the interrupt services routine at the memory location that the jump table specifies.
In VXI systems (and all Nationwide Instruments VXI/VME Controllers), the status/ID is no longer a
vector. It is de-coupled from the processor operation. After the interrupt handler receives the
status/ID, controller software invokes the appropriate support subroutine and passes the
status/ID value towards the subroutine.
The general format with the status/ID for a Register-Based VXI gadget is shown
within the following table.
Table II. General Status/ID Format for VXI Bus Devices

Bits
31-16
15-8
7-0
Contents
Device-Dependent
Cause/Status
(Device-Dependent)
Logical Address
of Interrupter
For Message-Based VXI devices, there is a further definition of the status/ID format. The status/ID can take on either a Response format or an Event format. Under the Event Format, bit 15 of your status/ID must be set. The values of status/ID bits 8 through 14 define the Event condition. The VXI bus specification currently defines these bits for three particular events. It also defines a syntax for defining your own events. The events defined within the VXI bus specification and their corresponding values for status/ID bits 8 through 15 are listed under.
No Cause Given (0xFF) - This event is sent by a Register-Based device that has only 1 reason to signal its Commander. Usually, this event is issued when an operation completes.
Request True (0xFD) — This event is sent by a gadget when the system requires service.
Request False (0xFC) — This event is sent by the device when the device no longer requires support. The VXI bus specification also defines a syntax for sending user-defined
events. This format specifies that bit 15 must be one and bit 14 must be 0. Bits 8 – 13 can then be utilized to specify a user-defined event, as shown inside the following table.

Table III. Message-Based System Status/ID—User-Defined Event Format

Bits
31-16
15
14
13-8
7-0
Contents
Device-Dependent
1
0
User-Defined Event
Logical Address
of Interrupter
Except for defining the lower 8 bits of your status/ID value to be the logical address of the interrupter, the VXI bus specification defines only a few particular values from the status/ID. Usually,Buy Windows 7, when you are working with a device capable of producing interrupts, you need to refer for the documentation accompanying the device to see what meaning, if any, the other bits of your status/ID have. Often, you control the conditions under which the interrupt is generated,Windows 7 Enterprise Sale, and also the genuine status/ID is not important because you will know in advance why the device is sending interrupts.

Signals
Instead of asserting an interrupt line, some devices can request services by producing a signal. "Signal" in this context is not an electrical signal (such as the backplane signals discussed earlier from the course),Windows 7 Starter Key, but rather a write of a 16-bit value to the signal register of another gadget. The signal register is simply a VXI configuration register that has a value written to it by another system capable of taking control from the bus. Not all devices implement a signal register. The term signal originates from its use in UNIX, where a signal is a means of inter-process communication. To use signals, the following two conditions must apply:
The signaling device must be able to take control of the VXI bus The system to which the signal is being sent must implement a signal register.
The signaling gadget uses the Data Transfer Bus to write a 16-bit value to the signal register, which is located at offset 8 from the configuration registers for the device being signaled. The 16-bit value has exactly the same format as the 16-bit status/ID.
The procedure for handling a signal through software is the same as for an interrupt. The processes discussed above for signals along with the interrupt cycle happen completely on the hardware level. These processes are transparent to a user’s application. When a controller senses an interrupt or sees that its signal register has been written to, the controller generates a local processor interrupt that lets the software driver know the event has occurred.