Yonah
Yonah core Intel Core Duo processor, codename. Yonah core with dual core CPU's are single-core Core Duo and Core Solo, Celeron M also used another this core, Yonah, Intel launched in early 2006.
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general overview of the basic concepts of technical analysis of good interface design Smart Cache Design Enhanced Intel Deeper Sleep technology optimized wireless network card configuration does not support power management 64bit instruction set and Intel's Hyper Threading Technology Technical Comparison of Yonah Intel Yonah and Merom testing and evaluation with the new Dothan processor interface of the same size, double the basic concept of the kernel is a single / dual-core processor core types, and its application is characterized by great flexibility , both for the desktop platform, can also be used for mobile platforms; both for dual-core, can also be used for single core. Yonah core mobile platform from Pentium M processor, the famous fine structure, with fewer pipeline stages, the implementation of high efficiency, powerful performance and low power consumption and so on merit. Yonah core using 65nm manufacturing process, the core voltage according to different versions about the 1.1V-1.3V, packages using PPGA, improved interface type is a new version of Socket 478 interface (with the previous Socket 478 desktop is not compatible.) Frequency of the front-side bus, Core Duo and Core Solo are 667MHz, while the Yonah core Celeron M is 533MHz. In terms of secondary cache, Core Duo and Core Solo are 2MB, and the Yonah core Celeron M is 1MB. Yonah core support hardware anti-virus technology and energy saving technology EDB EIST, and most models support the virtualization technology Intel VT. But the greatest regret is that does not support 64-bit technology, just 32-bit processors. It is noteworthy that, for the dual-core Core Duo, its has 2MB secondary cache in the X86 processor architecture is different from all other processors are all the X86 has two separate cache per core, and Core The Yonah Core Duo is the use of IBM's multi-core processors with a similar program ---- two core shared cache 2MB of secondary cache,
air force 1 shoes! Secondary cache shared with Intel's This is strictly true dual-core processor! Yonah core shared cache compact coupling scheme, the advantage of the ideal performance, disadvantage is that technology is more complex. However, according to Intel's plans, subsequent Intel processors each platform will be fully transferred to the Core architecture, Yonah core fact is the core of a transitional type, from the third quarter of 2006, which will be the desktop platform Conroe core replaced by a mobile platform will be replaced by the Merom core. Compared to Merom Yonah, the pipeline from the original 13 to 14 level, frequency of play in enhancing the role of buffer areas, Merom 4MB and 2MB of L2 is divided into two versions, and Yonah is consistent, regardless of 4MB or 2MB , shared by the dual-core, dual-core computing needs so that data can be shared. However, in terms of L2 cache is accessed, Merom has 8-way upgrade from Yonah? 6 Road (Athlon 64 is also 16.) Decoder side, Merom Yonah than the addition of a Simple decoder, so that further improve the decoding efficiency. However, in terms of complex operations, AMD Turion 64 built-in 3 Complex decoder will be more better (for example, scientific computing in Science Mark 2.0); instruction set terms, Merom in Yonah's Micro Fusion (micro-instruction set integration) technology based on higher level, add the Macro Fusion (macro set integration) technology. This macro than micro-instruction set of fusion sets more extensive integration of technology, such as If and Jump instruction combination, to increase the efficiency; execution unit area,
air force 1 high, Merom Yonah more than an FPU and an IEU (IEU is our usual said ALU), so in a clock cycle, you can transfer to the execution unit 3 microinstruction set, but can only transfer Yonah 2. However, among the three FLU, there is a fixed distribution of tasks. Floating point multiplication implementation must be the third FPU, floating-point add operation can perform only by the second, while the floating-point subtraction is relatively free, as long as the second and third FPU is idle, or idle the next cycle to be able to use the. In addition, the transmission channel 64-bit Yonah rose from 128, so that an SSE3 instruction to execute, then it has only one clock cycle. Technical analysis overview Yonah dual core with 1 million 5 thousand 1 million transistors Pentium M low to maintain the 14-stage pipeline structure, so the frequency although only 2.16GHz, but it is fast approaching the performance of more than 3GHz Pentium D dual-core processor, the core with 2MB L2 Cache for the internal core with the use of two, called Intel Smart Cache technology, will help to reduce the old Intel dual-core architecture that appears to read the serious delay in Cache, in addition to the core in particular to strengthen the SSE/SSE2 Micro Ops Fusion transportation management capabilities, but also for the first time to join in the action SSE3 instruction set processor, the main performance improvement for multimedia, while also Floating Point part of the degree of strengthening the implementation of enhanced 3D gaming effects. FSB area, Yonah will be the core of the previous generation Pentium M Dothan 533MHz FSB increased to 667MHz FSB, with higher bandwidth to cope with dual-core lead to greater data transfer. Yonah's first to support Intel Virtualization is also a function of the mobile processors, which can make the system able to support multiple operating systems at the same time, unfortunately it does not support the EM64T feature, be the only fly in the ointment. Although a low-power 65nm performance,
air force one low, but because of the dual-core Yonah has increased because the number of transistors and power consumption than previous generation single-core Dothan higher, to improve battery life, Intel has joined the Enhanced Intel Deeper Sleep function, to reduce unnecessary power consumption, so that the actual use of Yonah dual-core Dothan roughly the same time with the previous generation. Interface design core Yonah Pentium M 478 pins and pin definition to the previous generation Pentium M's 479pins slightly different, even single-core version of Yonah may not be able to run in the i915G/PM chipset. In addition, Intel announced earlier Yonah processor data, its processor interface mPGA 478 or BGA 479, so many readers will think the old Yonah compatible with the Pentium 4 Socket 478 motherboards, but we look on the map contrast, Pentium 4 processor and the Pentium M Yonah pin arrangement of the core is not the same, and thus are not compatible. Pentium M Yonah dual-core processor, the internal architecture made a substantial improvement, the new Smart Cache architecture effectively enhance the efficiency of dual-core, dual-core design of the traditional core of each individual has its own L2 Cache, but the Yonah dual- Smart Cache is the core structure of the core through internal Shared Bus Router share the same L2 Cache, so when the CPU 1 after the operation the result when there is L2 Cache, CPU 0 can be read through the Shared Bus Router on CPU 1 shared L2 Cache on the data, significantly reducing the read latency and reduce the use of the FSB bandwidth, but also adding L2 & DCU Data Pre-fetchers and Deeper Write output buffer memory, an increase of Cache hit rate. Even the current dual-core L2 Cache K8 architecture, the design is not as Smart Cache, because the shared L2 Cache Cache Misses further reduce the case, when reading their own CPU 0 L2 Cache, found no data will be required sum L2 Cache CPU 1 reads the data, the situation is the same as CPU 0 of L3 Cache, and the shared L2 Cache design has none of the above needs. Excellent Smart Cache Design Smart Cache Architecture There are many different benefits, such as when two cores when the workload does not mean, if the independent L2 Cache, dual-core architecture including a core of the opportunity to work there too little, L2 Cache is not effective application, but also because of a core of heavy workload L2 Cache, L2 Cache capacity can not meet the needs of system memory to spend, we should note that it does not borrow another one core L2 Cache space,
air force one shoes, but SmartCache they do not have this problem because the L2 Cache is shared. Shared Bus Router addition to more effectively deal with L2 Cache read, it will also transfer to dual core when using FSB schedule, the newly added Bandwidth Adaptation mechanisms to improve the FSB dual-core shared the efficiency and reduce unnecessary delays, in fact, this Shared Bus Router design is a bit like the K8 the System Request Interface and Crossbar Switch purposes. In addition, SmartCache mobile processor architecture is also used in a great advantage, for example, the system is idle or not much work, Yonah processor core can be one of them off to reduce the processor power, but it 2MB L2 Cache operation can be maintained is to keep working, and Shared Bus Router can also be due to changes in demand L2 Cache L2 Cache size, switch off the unnecessary part of L2 Cache to reduce power consumption, but in a separate double L2 Cache core, if you want one of the Cache off, it certainly needs to which a transfer of the core data from L2 Cache, and Cache and the core will also be closed, but also real-time response to the demand can not change or turn off the part of the L2 Cache capacity to reduce power consumption. Enhanced Intel Deeper Sleep technology generation Pentium M Yonah dual-core processor, will be added to the enhanced sleep mode called Enhanced Intel Deeper Sleep, idle in the C-State in the new enhanced version of the C4 model. Previous years, the processor Pentium M processor can be idle until, by the Active C0 C1 active state into the HALT mode the moratorium, the frequency of slow processor, and then further by entering STOP CLOCK HALT C1, so the processor to stop working completely, When the processor for some time in the STOP CLOCK state has not been recovered from, the system will enter C3/C4 of the Deep Sleep and Deeper Sleep state. Deep Sleep and Deeper Sleep to stop working in the processor to lower voltage to further reduce power consumption so batteries live longer, but can not completely stop the processor because the processor stop working, but in fact the processor's L1 and L2 also store the data, the whole processors will make the L1 and L2 turning off data loss, can not turn the system back from the Deep Sleep state to Active, but a new generation of dual-core processor Yonah Pentium M's support for the Enhanced Intel Deeper Sleep L1 and L2 data backup into the system memory, so the processor can be completely stopped, as long as necessary, L1 and L2 memory system data can be restored to the processor, Intel disclosed Enhanced Intel Deeper Sleep Deeper Sleep power than the 30 % or more. Wireless network card configuration on the wireless card 2915ABG INTEL replace the existing new 3945ABG, 3945ABG more compact size, only half the size of the original 2915ABG, which for those small and thin portable notebook is indeed good news, and for not meaningful to ordinary laptops, while the more integrated 3945ABG, 2915ABG need a piece of original manufacture nearly 300 components, is now in the 3945ABG as long as 90 can get. Basically, 3945ABG 2915ABG is a modified version of the existing, small differences in details, specifications, improved focus on signal processing and WoWLAN (Wake on WLAN), and like a lot of media fuss about the Cisco Compatible Extensions (Cisco extended the safety norms ), in fact, Intel is now the product has supported. However, wireless networks, easy to use software is very important, but often overlooked by people, especially now that wireless network security issues have been paying attention, but if not side-to-use security settings, led to little interest, equal to not solve the problem. From this perspective, 3945ABG most importantly, than the Intel PROSet / Wireless Software v10.0, as well as support and the use of Cisco Business Class Wireless Suite (commercial grade wireless network software suite), and Avaya's SIP Softphone (SIP protocol software Internet telephony), which will improve safety, ease of use and availability of wireless VOIP. Yonah optimized power management product line includes standard-voltage version is basically (SV: Standard Voltage), Low Voltage (LV: Low Voltage), Ultra Low Voltage (ULV: Ultra Low Voltage) power consumption in three different versions This is the same as the division of Dothan. Intel said the TDP will be on the OEM manufacturers has increased, mainly due to the impact of dual-core, SV version is 31W (of the current version of Dothan is 27W), LV version of 15W (of the current version of Dothan is 12W). However, the average drive time of the battery power consumption compared with the current estimate Dothan is not much change. If the platform does not increase the overall average power consumption if compared with the Sonoma is actually improved. Support the claim there are several main reasons, first of Yonah's power-saving technology is significantly improved through the introduction of Intel Dynamic Power Coordination called the power-saving technology, through this technology, the two core switches to power saving mode can simultaneously control can be controlled separately. CPU according to the state of the OS provides several power-saving mode. Such as the Banias generation of processors is divided into C0 (general use), C1 (Halt instruction standby time of entry into force), C2 (frequency of stops), C3 (sleep), C4 (more sleep), and other 5 state. Yonah's two cores to the core of the CPU according to their load, switch the power saving mode alone,
nike air force one high, but also can enter into the same mode. Such as the CPU's processing capacity is not too much, and when in battery mode, in which a core, C0 (general use) mode while the other core can be a C2 (stop frequency) operation. However, as the two core Yonah were not configured to provide frequency PLL and voltage converter (VoltageRegulator), so a single core CPU can not separate the need to reduce the voltage into the C3 or C4 model, can not use the CPU voltage / frequency needs to be changed SpeedStep technology In general just can not use two core voltage / frequency control method for necessary saving were because of the need 2 voltage converter and PLL. Does not support 64bit instruction set and support the development of Hyper Threading technology, code-named Yonah Vanderpool technology, Intel Virtualization Technology, but always known as the X64 does not support the 64bit instruction set EM64T and Hyper Threading technology (HT). In this regard Intel mobile platform mobile business group of Rama explained, Support is also a matter of course X64, X64 for 64bit support for both the original software only to target high-end workstations. The only two memory slots for notebook computers, the need to increase to 4GB memory capacity required to process much longer than the desktop confidential, so this choice is quite reasonable. In fact, generation after Merom mobile processor, has already begun to support both technologies. Intel Yonah and Merom technical comparison following the server and desktop processor Conroe processors WoodCrest market after another, the next-generation mobile processor Merom Core microarchitecture is also the official debut, though Intel claims the new Core micro-architecture integration of Mobile-based high efficiency and energy saving Netburst previous generation desktop, functions, and to optimize for multi-core applications, but the Core micro-architecture is difficult to find the slightest shadow of Netburst, because nearly 90% of its design is based on Yonah Mobile architecture make improvements, retaining only Netburst architecture Prefectching, This is clearly hoping for the previous generation of Intel's failure to give the perfect Netburst the next step. Although the Intel Core micro-architecture is based on the Yonah core of the Mobile platform design, but there are more than 7 percent of the structure and the line is re-refined and added five major reforms, including Intel Wide Dynmaic Execution, Intel Intelligent Power Capability, Intel Advanced Smart Cache, Intel Smart Memory Access, and Intel Advanced Digital Media Boost. Intel Wide Dynamic Execution - Merom processor with 4 Decoder (3 Simple decoders + 1 Complex Decoders), more than the previous generation Yonah core group 1 (2 Simple Decoders + 1 Complex Decoders) can handle a set of Simple Coder multiple instructions, and further improve the efficiency per cycle, and increasing processor energy efficiency. While Merom's Pipeline Stage 13 Stage by the Yonah's rose slightly to 14 Stage, but the Branch Predictor Bandwitdh Merom upgrade 20Bytes (Yonah is 16Bytes), so the branch prediction capabilities and accuracy of the efficiency remains similar. In addition, Merom processors not only retained the Micro-op Fusion technology,
air force one low nike, and also added a new Macro-Fusion technology, in the old generation micro-architecture, each instruction is sent when the movement for its decoding and execution are completely independent , but the Intel Core micro-architecture allows common instruction set, such as a Compare instruction with then have a Jump instruction, combined into a single Micro-Op instructions, making the Merom processor in a particular case has operations per cycle 5 set of instructions, according to Intel, said the majority of x86 programs, about every 10 to 15 there will be a set of instructions through the Macro-Fusion can be combined, thus reducing the computation time required for program execution, but will not improve performance increase the processor's power consumption, Intel also improved this ALU (Arithmetic Logic Unit) to support the Macro-Fusion part of the technology. Intel Intelligent Power Capability - Merom Yonah processors significantly enhance the contrast the number of transistors, power consumption will be relatively increased, while Merom processors for the order at a reasonable level of performance and power consumption, Merom added Ultra Fine Grained power design, fine independent switch logic control functions of the operation unit, will be opened only when necessary to avoid unnecessary power consumption when idle waste, known as the Sleep Transistors technology, in addition, the core of all Buses and Array with independent control of the VCC voltage, When this part is idle, it will be operating in low power mode, so the performance of Merom processor power consumption can be maintained, and Yonah processors similar. Intel Adcanced Smart Cache - early in the Yonah processor, Intel has joined the Smart Cache architecture, through the core within the Shared Bus Router share the same L2 Cache, the Prefetch Merom further strengthen capacity, each with three cores are independent Prefetchers (2 Data and & 1 Instruction) and 2 L2 Prefetchers, can simultaneously detect the Multiple Streaming and Strided Acess Patterns, L2 Cache than the Yonah doubled to 16-Way 256Bit 4MB capacity, but Latechy was maintained at 12-14ns of , the order processing Cache Merom architecture to further improve performance. Intel Smart Memory Access - In order to enhance the efficiency of memory reads, Merom processor reads the memory by adding a new technology called Memory Disambiguation, Out of Order through the reading order of the process to analyze the memory, when that data is completely independent of a , you can perform it earlier in order to reduce the waiting time to reduce the processor idle, while reducing memory read latency value. Intel Adavanced Digital Media Boost - Merom processors have 128Bit-SIMD interger arithmetic and 128bit SIMD double precision Floating-Point Operations. Only 64Bit traditional processor design of the SIMD interger arithmetic and Floating-Point Operations, so in the implementation of 128Bit the SSE, SSE2 and SSE3 instructions, instructions need to be split into two 64Bit instruction, and the need for two frequency cycle is complete, but Core micro-architecture only needs a frequency can complete the swap, the Executive into the efficiency up to 1 times the current SSE instruction set has been very widely used in mainstream software, including graphics, images, audio, encryption and mathematical calculations, etc. use, single-cycle 128Bit processor means other than the ability to enhance the performance of the frequency, so that the processor has high energy efficiency performance. Intel Yonah and Dothan Yonah improvement relative to the Dothan: Yonah relative to the Dothan most obvious improvement is its dual-core. However, as Yonah 65nm process is used, so although there are two dimensions of the core, but it was and as big as a Dothan core. In other words, Intel to create a dual core Yonah and manufacture of single-core Dothan is almost the same cost. Said the main reason is not its size, in fact, although there are two core Yonah, but its secondary cache is still 2M. And Pentium D different, Yonah of 2M is not separated into two secondary cache secondary cache 1M, but a complete dual-core 2M shared secondary cache. This is a very important distinction, which means that the two Dothan Yonah is far from simple merge. Major performance improvements Yonah around SIxx FP and FP performance, which is the current Pentium 4 Dothan and compared the two biggest weaknesses. There are three improvements: First, the improvement is, Yonah SSE decoder can decode instructions regardless of the type of instruction. The width can improve the decoding speed improved processor performance. Followed SSE/SSE2 run, the current Yonah can use Micro Ops Fusion engine, which can be beneficial to enhance performance and low power consumption. Yonah's two cores support the SSE3 instructions, very similar to the Pentium 4 E (Prescott). Third, Yonah's floating point performance has also been some improvements, improved floating point performance of the gaming performance of the processor has a very big impact. Yonah and Dothan performance comparison test: Yonah's performance in practice than in Dothan whether there much improvement, I think this is one very interesting question. Then we have the performance of the Yonah and Dothan to conduct a comparison test, but unfortunately because of our Yonah is the frequency of 2.0GHz, while the frequency for Dothan contrast is 2.13GHz. Therefore, we can not get a fair performance comparison with the frequency. First, we test the response time is the cache, using ScienceMark 2.0, this test did not affect the level of the clock frequency. Can be seen from the chart of a cache Yonah and Dothan as reaction time, but the secondary cache slower than Dothan. I think this may be due to Yonah secondary cache using the latest dynamic adjustment of technical reasons. This technology is to reduce power consumption of the dual-core optimized shared secondary cache, a time of low demand in the system Yonah will automatically adjust the size of the secondary cache, so that the slower secondary cache response time. 1, the highest frequency of the Yonah dual-core processor, the Sonoma platform performance than the highest frequency of Dothan core processor (2.26GHz) 68% higher than 2 cards in the same configuration, the maximum frequency dual-core Yonah processor in Quake 4 test frame rate to 76FPS, while the 2.26GHz of the Dothan core processor performance only 41FPS - Yonah processors Dothan processor, the average increase in FPS performance 50% ~ 70% 3, Yonah dual-core processor front side bus increase to 667MHz, while the Dothan core processor is only 533MHz 4, in the PCMark05 test, the highest frequency of the Yonah dual-core processor, Sonoma platform, the score of the highest frequency of Dothan core processor (2.26GHz) 31% higher than 5, in 3DMark05 test, the highest frequency of Yonah dual-core processor, Sonoma platform, the score of the highest frequency of Dothan core processor (2.26GHz) 105% higher than 6, in the SPECint test (test processor integer performance), the highest frequency of Yonah dual-core processor, Sonoma platform, the score of the highest frequency of Dothan core processor (2.26GHz) 68% higher than the Yonah dual-core processor performance despite power, but Intel has the power, and there is no clear position on the issue. When asked about the Napa platform, compared to Sonoma platform, battery or change a variable length short, Intel said that as the use of Napa notebook platform is not yet complete, said concrete results is unclear. Intel Napa platform, but want to use the time the battery can be more than the Sonoma platform, Intel Yonah processor power that, although higher, but the relevant parts of the electricity usage increased by 28% or more, this time to improve the battery life has created a favorable conditions. Wish to use Intel Napa platform 14,15 inch laptop battery standard can use time to 5 hours. Testing and evaluation in the new Intel Yonah processor interface used on the new interface, it is not compatible with the Pentium M. When the introduction of Pentium M, Intel also introduced a new processor interface, Socket 479, Pentium 4 was used than the Socket 478 多 needle, the needle is completely dispelled the Pentium M used in the Pentium 4 the possibility of on the motherboard. Although the number of pins and the Pentium M Yonah is the same, is 479, but the layout is completely different, which also did away with the two processors can not use the same motherboard, not to mention chipsets compatible. The same size, twice the core relative to the Dothan, Yonah most obvious improvement is the dual-core. Benefit from the 65nm manufacturing process, the Yonah dual-core and single core Dothan core area of the same, which means the production of Intel Yonah little different than the cost of Dothan. Do not increase the nuclear area, another important reason for not increasing the secondary cache, and Dothan as is 2MB. Pentium D with different, Yonah in 2MB of secondary cache of 1MB is not divided into two separate cache, two cores share 2MB secondary cache. This is a very important differences, means that Yonah is not simply glued together two Dothan. Improved focus on core Yonah floating-point operations, this is the Pentium 4 Pentium M than the lame place. The first improvement is Yonah three decoders are able to perform various types of SSE instructions, the processor bandwidth to increase the decoder can greatly improve overall performance. Secondly, all SSE and SSE2 operations are able to use the micro-ops fusion Yonah (Micro Ops Fusion) engine. This improvement in performance while maintaining low power consumption. However, the performance of the specific details of Yonah large number of products can only be listed next year to get after. Another aspect of the improvement is Yonah's two cores will support SSE3, like the Pentium 4E (Prescott). In addition to these, Intel has also taken many measures to improve floating point performance, while the floating-point operations is mainly used for games, shows Intel Yonah on the intent of such a far-reaching effort. SSE and floating-point operations together to improve Intel Digital Media Boost. The name of the future may be as funny as MMX, but there is still very shocking. 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